DDR/LPDDR(5,4,3) PHY & Controller, up to 6400Mbps

性能领先的INNOSILICON DDR PHY支持DDR5/LPDDR5 DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR,包含PHY和控制器IP,速度高达6400Mb/s,并且支持任何总线宽度。

经过量产和测试芯片验证的芯片,DDR PHY具有低功耗和小尺寸。这种紧凑的面积转化为低I/O引脚数,简化了封装基板和PCB,同时可支持只采用2层的板级布线。

利用DFI V2.0/V2.1/V3.0/V3.1/V4.0/标准的选择,DDR PHY可以与ayx爱游戏体育网页登录入口科技自己或主要兼容的第三方内存控制器集成。它通过APB完全寄存器控制,通过高速BIST、环回模式和边界扫描简化了生产测试。

DDR PHY采用独立的模块化设计,包含I/O、ESD、定时同步模块DLL,可扩展至几乎无限的总线宽度。可选组件包括特定于客户的总线宽度、集成PLL、自定义引脚以及支持AHB/AXI和FIFO接口的Innosilicon DDR内存控制器。我们提供定制的DDR解决方案,以满足您的需求,同时根据您的需要完成任何级别的集成支持。

The performance leading INNOSILICON DDR PHY supports DDR5/LPDDR5 DDR4/LPDDR4/DDR3/LPDDR3/DDR2/LPDDR2/DDR at speeds up to 6400Mb/s and in any bus width.

Silicon proven in mass production and test chips, the PHY combines low power consumption with its small size. This compact form factor is translated into low I/O pin count, simplifying both package substrate and PCB, while potentially allowing for board level routing with only 2 layers.

Leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1/V4.0/ standards, the PHY can be integrated with memory controller from our own or major compatible 3rd parties. It is fully register controlled via an APB and the production testing is simplified through high-speed BIST, loopback modes, and boundary scan.

With a self-contained yet modular design, the PHY contains the I/Os, ESD, a timing synch module DLLs and can be expanded to a virtually unlimited bus width. The Optional components include customer specific bus widths, integrated PLLs, custom pinouts, and the Innosilicon memory controller which supports AHB/AXI and FIFO interfaces. We provide custom DDR solutions to meet your needs while handling whatever level of integration support as you required.

KEY FEATURES:

  • Fully compliant with DDR5/LPDDR5/DDR4/LPDDR4/DDR3 /LPDDR3/DDR2/LPDDR2/DDR JEDEC SDRAM standards

  • Silicon proven in 14, 28, 40, 55, 65, 90, 130 and 180nm across SMIC, TSMC, Samsung, UMC and Global Foundries

  • Low power, small area, scalable design

  • Supports speed up to 6400 Mb/s

  • LVSTL, SSTL_15, SSTL_18, POD_12, POD_11, HSUL_12

  • Programmable output drive strength for power saving and to support RDIMM or UDIMM

  • Master and Slave DLLs for precise timing management with fine grain adjustment

  • Accommodates, but is not limited to, industry standard x4, x8, x16, x32 SDRAM widths and depths

  • Support DDR5 dual channel mode, dual 32bit data +8bit ECC

  • Support Write FFE and Read DFE equalization

  • Independent read and write timing adjustments with auto calibration, dynamic V&T tracking

  • Both Read and Write Per bit deskew support

  • Support over 10 training modes, like CA training, CS training, and write leveling training

  • Support maximum 4 frequency points for fast frequency change

  • Supports point to point memory sub systems and multi-rank

  • Support both Write and Read CRC

  • Low power operation with optimal power management features including deep power down and self-refresh

  • Optimized look ahead command management to reduce system overhead

  • Embedded BIST logic for at-speed production test

  • Optional PCB SI simulation services

  • Optional memory controller that supports efficient AXI/AHB CPU bus and power saving modes

INNOSILICON ADVANTAGES:

  • Fully customized solutions including Controller and PHY

  • Over 500,000 wafers shipped out with Innosilicon DDRn IP

  • Ported to over 50 process nodes in SMIC, GF, TSMC, GF and other foundries, including all FinFET nodes

  • Full harden PHY proven by 100+ tapeouts

  • Simple integration with pre-assembled PHY

  • Low IO pin count

  • High performance

  • Test chip and FPGA integration services available

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

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